1. Field of the Invention
This invention relates to a delay apparatus and method for delaying a digital signal for a predetermined delay period of time
2. Description of Related Art
A conventional delay apparatus is disclosed in Japanese laid-open patent application 63-224411. FIG. 9 is a block diagram showing the conventional delay apparatus. The delay apparatus of FIG. 9 comprises a rising edge detection circuit 101, an RS flip-flop 102, a frequency demultiplier 103, a counter 104, a comparator 106, a read only memory (ROM) 107, and a decoder 108. In FIG. 9, the rising detection circuit 101 detects the rising edge of the digital signal A, and outputs an edge detection signal D. The RS flip-flop 102, a frequency demultiplier 103, and a counter 104 are reset by the edge detection signal D. After the counter 104 is reset by the edge detection signal D, the counter 104 increments its own count value. The comparator 106 outputs a detection signal E if a value stored by the ROM 107 equals to a count value of the counter 104. The RS flip-flop 102 is set by the detection signal E.
The operation of the conventional delay apparatus shown in FIG. 9 is described by using FIG. 10. FIG. 10 is a timing chart showing the operation of the conventional delay apparatus. In FIG. 10, time is plotted on the horizontal axis. As shown in FIG. 10, the rising edge of the digital signal A is delayed for a delay period of time T which is set at various values by the decoder 108 and the ROM 107.
As described above, the conventional delay apparatus can achieve a highly stable and accurate operation without fluctuation by time elapsing, because the conventional delay apparatus sets the delay period of time T by means of an accurate digital clock signal.
As shown in FIG. 10, in the conventional delay apparatus shown in FIG. 9, the rising edge of the digital signal A can be provided the delay period of time, which is a pulse signal B of the RS flip-flop 102. However, the falling edge of the digital signal A can not be provided the delay period of time T. Hence, the conventional delay apparatus can not output the pulse signal B the period of time while which maintains the level “1” is equal to the period of time while the digital signal A maintains the level “1”. Hence the conventional delay apparatus can not operate in the system using not only the rising edge but also falling edge of the output pulse signal B.